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S5N8947 mcu for dsl data sheet rev 1 . 8 oct. 25 , 2001 samsung electronics co., ltd.
S5N8947 (mcu for dsl) electronics dsl group page : 2 october 26 , 2001 rev 1.8 samsung electronics important notice samsung reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current.
electronics S5N8947 (mcu for dsl) page : 3 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential contents 1. general desc ription ................................ ................................ ................................ ................................ ............................ 5 2. features ................................ ................................ ................................ ................................ ................................ ........................ 6 3. functional block descriptions ................................ ................................ ................................ ................................ .. 7 3.1. b lock d iagram ................................ ................................ ................................ ................................ ................................ 7 3.1.1 mode 1 (1 sar + 1 mii + 1 usb) ................................ ................................ ................................ ......................... 7 3.1.2 mode 2 (1 sar + 2 mii + 1 usb) ................................ ................................ ................................ ......................... 8 3.2. a rchitecture ................................ ................................ ................................ ................................ ................................ .. 9 3.3. s ystem m anager ................................ ................................ ................................ ................................ ............................ 9 3.4. u nified i nstruction /d ata c ache ................................ ................................ ................................ ............................ 9 3.5. sar/utopia i nterface ................................ ................................ ................................ ................................ ................ 9 3.6. ethernet ................................ ................................ ................................ ................................ ................................ .......... 9 3.7. usb c ontroller ................................ ................................ ................................ ................................ ........................... 10 3.8. dma c ontroller ................................ ................................ ................................ ................................ ......................... 10 3.9. uart ................................ ................................ ................................ ................................ ................................ .................. 10 3.10. t imers ................................ ................................ ................................ ................................ ................................ ........... 10 3.11. p rogrammable i/o ................................ ................................ ................................ ................................ ................... 10 3.12. i nterrupt c ontroller ................................ ................................ ................................ ................................ .......... 10 3.13. i 2 c s erial i nterface ................................ ................................ ................................ ................................ ................ 11 3.14. spi ................................ ................................ ................................ ................................ ................................ ................... 11 3.15. pll s ................................ ................................ ................................ ................................ ................................ ................ 11 4. pin descriptions ................................ ................................ ................................ ................................ ................................ .... 12 4.1. p in c onfiguration ................................ ................................ ................................ ................................ ....................... 12 4.2. l ogic s ymbol d iagram ................................ ................................ ................................ ................................ ............... 13 4.2.1 mode 1 (1 sar + 1 mii + 1 usb) ................................ ................................ ................................ ....................... 13 4.2.2 mode 2 (1 sar + 2 mii + 1 usb) ................................ ................................ ................................ ....................... 14 4.3 p in d escriptions with the p in number and p ad type ................................ ................................ ................... 15 4.4 pad d escriptions ................................ ................................ ................................ ................................ ......................... 18 5. operation desc ription ................................ ................................ ................................ ................................ ..................... 19 5.1. cpu c ore o verview ................................ ................................ ................................ ................................ ...................... 19 5.2. i nstruction s et ................................ ................................ ................................ ................................ ............................ 20 5.3. o perating s tates ................................ ................................ ................................ ................................ ........................ 21 5.4. o perating m odes ................................ ................................ ................................ ................................ ......................... 21 5.5. r egisters ................................ ................................ ................................ ................................ ................................ .......... 21 5.6. e xceptions ................................ ................................ ................................ ................................ ................................ ...... 22 6. hardware structur e ................................ ................................ ................................ ................................ ........................ 23 6.1. s ystem m anager ................................ ................................ ................................ ................................ .......................... 23 6.1.3. overview ................................ ................................ ................................ ................................ ................................ . 23 6.1.4. system manager registers ................................ ................................ ................................ ................................ .. 23 6.1.5. system memory map ................................ ................................ ................................ ................................ ............. 25 6.2. i nstruction / d ata c ache ................................ ................................ ................................ ................................ ........ 27 6.3. i 2 c b us c ontroller ................................ ................................ ................................ ................................ ...................... 28 6.4. ethern et c ontroller ................................ ................................ ................................ ................................ .............. 29 6.4.1. block diagram ................................ ................................ ................................ ................................ ...................... 29
S5N8947 (mcu for dsl) electronics dsl group page : 4 october 26 , 2001 rev 1.8 samsung electronics 6.4.2. features and benefits ................................ ................................ ................................ ................................ ........... 29 6.5. sar and utopia i nterface ................................ ................................ ................................ ................................ ...... 31 6.5.1. block diagram ................................ ................................ ................................ ................................ ...................... 31 6.5.2. features and benefits ................................ ................................ ................................ ................................ ........... 32 6.6. usb c ontroller ................................ ................................ ................................ ................................ ........................... 33 6.6.1. block diagram ................................ ................................ ................................ ................................ ...................... 33 6.7. dma c ontroller ................................ ................................ ................................ ................................ ......................... 34 6.8. uart ................................ ................................ ................................ ................................ ................................ ................ ..35 6.9. t imers ................................ ................................ ................................ ................................ ................................ ................ 36 6.10. i/o p orts ................................ ................................ ................................ ................................ ................................ ....... 37 6.11. i nterrupt c ontroller ................................ ................................ ................................ ................................ .......... 38 6.12. spi ................................ ................................ ................................ ................................ ................................ ................... 39 7. special function registers ................................ ................................ ................................ ................................ ........... 41 8. electric characte ristics ................................ ................................ ................................ ................................ .............. 45 8.1. a bsolute m aximu m r atings ................................ ................................ ................................ ................................ ... 45 8.2. r ecommended o perating c onditions ................................ ................................ ................................ ................. 45 8.3. dc e lectrical c haracteristics ................................ ................................ ................................ ............................. 46 9. package dimension ................................ ................................ ................................ ................................ .............................. 47
electronics S5N8947 (mcu for dsl) page : 5 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 1. general d escriptio n s amsung's S5N8947 16/32 - bit risc microcontroller is a cost - effective, high - performance microcontroller solution . the S5N8947 is designed as 2 - channel 10/100mbps ethernet controller for use in managed communication hubs and routers. the S5N8947 also prov ides atm layer sar (segmentation and reassembly) function with utopia interface and the full - rate usb (universal serial bus) function. the S5N8947 is built around an outstanding cpu core: the 16/32 - bit arm7tdmi risc processor designed by advanced risc mac hines, ltd. the arm7tdmi core is a low - power, general purpose, microprocessor macro - cell that was developed for use in application - specific and custom - specific integrated circuits. its simple, elegant, and fully static design is particularly suitable for c ost - sensitive and power - sensitive applications. important peripheral functions including an uart channel, 2 - channel gdma, three 32 - bit timers, watchdog timer, i 2 c bus controller, spi, and p rogrammable i/o ports are supported . built - in logic including an i nterrupt controller, dram controller, and a controller for rom/sram and flash memory are also supported . the S5N8947 ? s system manager provides an internal 32 - bit system bus arbiter and an external memory controller including control logic for a pcmcia sock et interface. to reduce total system cost, the S5N8947 offers a unified cache , 2 - channel 10/100mbps ethernet controller , sar and usb . most of the on - chip function blocks have been designed using an hdl synthesizer and the S5N8947 has been fully verified i n samsung's state - of - the - art asic test environment. item s5n8946 S5N8947 only one mode two modes are supported: mode 1. mii + utopia + usb mode 2. 2*mii + utopia + usb 2 timer 3 timer - 1 watchdog timer - spi interface support architecture - pcmc ia support utopia level 1 support utopia level 1/2 support seven wire support (10 mbps ethernet support) mii/seven wire support (10/100 mbps ethernet support) usb support byte access. usb support word access and dma operation. function sar support hardwired little endian . sar support hardwired big/little endian. 50 mhz operation 72 mhz operation performance 4k unified cache 8k unified cache operation condition 3.3v 1.8v package 240 qfp 208 lqfp table 1 s5n8946 vs. s5n89 47
S5N8947 (mcu for dsl) electronics dsl group page : 6 october 26 , 2001 rev 1.8 samsung electronics 2. features 8 - kbyte unified cache sar (segmentation and reassembly) utopia (the universal test & operations phy interface for atm) level 1/2 interface 2 - channel 10/100mbps ethernet full - rate usb controller 2 - ch gdma (general purpose direct memory acces s) uart (universal asynchronous receiver and transmtter) 3 programmable 32bits timers watchdog timer 18 programmable i/o ports interrupt controller i 2 c controller spi (serial peripheral interface) built - in plls for system/usb pcmcia ? memory and i/o ? master modes cost effective jtag - based debug solution boundary scan 3.3v i/os and 1.8v core supply voltage operating frequency up to 72mhz 208 lqfp package
electronics S5N8947 (mcu for dsl) page : 7 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 3. functional block descriptions 3.1. block diagram 3.1.1 mode 1 (1 sar + 1 mii + 1 usb) arm7tdmi 32bit risc cpu ice breaker cpu interface unified cache 4-word write buffer bus router 18 general i/o ports interrupt controller uart 32bit timer 0, 1, 2 gdma 0, 1 memory controller with refresh control tap controller for jtag 32-bit system bus 3-bank rom sram flash 4-bank dram 4-bank external i/o device external bus master ethernet mac usb interface pll* (usb) x'tal osc sar/utopia connection memory pll* (system) iic controller watchdog timer spi controller pcmcia i/f figure 1 top block diagram: mode 1
S5N8947 (mcu for dsl) electronics dsl group page : 8 october 26 , 2001 rev 1.8 samsung electronics 3.1.2 mode 2 (1 sar + 2 mii + 1 usb) arm7tdmi 32bit risc cpu ice breaker cpu interface unified cache 4-word write buffer bus router 5 general i/o ports interrupt controller uart (internal clock only) 32bit timer 0, 1, 2 gdma 0, 1 memory controller with refresh control system bus arbiter tap controller for jtag 32-bit system bus 3-bank rom sram flash 4-bank dram 2-bank external i/o device external bus master ethernet mac usb interface pll* (usb) x'tal osc sar/utopia connection memory pll* (system) iic controller watchdog timer spi controller ( 3 gpio pins ) ethernet mac figure 2 top block diagram: mode 2
electronics S5N8947 (mcu for dsl) page : 9 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 3.2. architecture integrated system for embedded ethernet / usb / sar fully 16/32 - bit risc architecture efficient and powerful arm7tdmi core little/big - endian mode is fully supported. (the internal register supports word access only.) cost - effective jtag - based debug solution supports boundary scan 3.3. system manager 8/16/32 - bit external bus support for rom/sram, flash memory, dram and external i/o one external bus master with bus request/acknowledge pins supports edo/normal or sdram programmable access cycle four - word depth write buffer cost - effective memory - to - per ipheral dma interface supports pcmcia ? memory and i/o ? master mode 3.4. unified instruction/data cache two - way set - associative unified cache (8kbytes) supports lru (least recently used) protocol 3.5. sar/utopia interface directly supports atm adaptation layer five (aal5) segmentation and reassembly segments and reassembles data up to 70mbps a glueless utopia level 1/2 interface is supprted ( for r eceiving and transmitting atm cells with sar, it is a standard atm interface between atm link and physical layer). 3.6. ethernet 2 - channel 10/100mbps ethernet controller 4 dma engines with burst mode full compliance with ieee standard 802.3 supports mii interface (7 - wire 10 - mbps interface is also supported).
S5N8947 (mcu for dsl) electronics dsl group page : 10 october 26 , 2001 rev 1.8 samsung electronics 3.7. usb controller supports 12mbps full rate function for univers al serial bus 3.8. dma controller 2 - channel general purpose dma (for memory - to - memory, memory - to - spi, spi - to - memory, uart - to - memory, memory - to - uart data transfers without cpu intervention) initiated by a software or a external dma request increments or decre ments source or destination address in 8 - bit, 16 - bit or 32 - bit data transfers 3.9. uart uart block with dma - based or interrupt - based operation supports 5 - bit, 6 - bit, 7 - bit, or 8 - bit serial data transmit and receive programmable baud rates infra - red (ir) tx/r x support (irda) 3.10. timers three programmable 32 - bit timers interval mode or toggle mode operation supports a watchdog timer 3.11. programmable i/o 18 programmable i/o ports pins individually configurable to input, output, or i/o mode for dedicated signals 3.12. interrupt controller 23 interrupt sources, including 7 external interrupt sources normal or fast interrupt mode (irq, fiq) prioritized interrupt handling
electronics S5N8947 (mcu for dsl) page : 11 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 3.13. i 2 c serial interface single master mode operation only 3.14. spi full duplex operation work with dat a characters from 4 to 32 bits long supports gdma mode for spi transmission and reception single master spi modes only supported programmable baud rate generator programmable clock phase and polarity 3.15. plls the external clock can be multiplied by on - chip p lls to provide high frequency system/usb clock the input frequency is fixed to 12 mhz the output frequency is 6 times the input clock for system the output frequency is 4 times the input clock for usb
S5N8947 (mcu for dsl) electronics dsl group page : 12 october 26 , 2001 rev 1.8 samsung electronics 4. pin descriptions 4.1. pin configuration S5N8947 208-lqfp-2828 (top view) b0size[0] b0size[1] unconnection nreset osc_xin osc_xo gnd36 xclk_i gnd1 filter_s filter_u vdd3/4 gnd3/4 extmreq extmack bigend mclko gnd5 unconnection vdd5 ntrst tms tck tdi tdo ndtack noe necs[0] necs[1] necs[2] necs[3] nrcs[0] nrcs[1] nrcs[2] vdd7/8 gnd7/8 nrcs[3] nras[0] nras[1] nras[2] nras[3] ncas[0] ncas[1] ncas[2] ncas[3] ndwe nwbe[0] vdd9 gnd9 nwbe[1] nwbe[2] nwbe[3] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 data[21] data[20] data[19] gnd17 vdd17 data[18] data[17] data[16] data[15] data[14] data[13] data[12] data[11] data[10] data[9] data[8] gnd15/16 vdd15/16 data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] a ddr[21] addr[20] addr[19] addr[18] addr[17] gnd13/34 vdd13/34 addr[16] addr[15] addr[14] addr[13] addr[12] addr[11] addr[10] addr[9] addr[8] addr[7] addr[6] addr[5] addr[4] vdd11 gnd11 addr[3] addr[2] addr[1] addr[0] 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 uto_rxd[0] uto_rxadr[1] uto_rxadr[0] gnd25 vdd25 uto_txclav uto_txenb uto_txsoc uto_txd[7] uto_txd[6] uto_txd[5] uto_txd[4] uto_txd[3] uto_txd[2] uto_txd[1] uto_txd[0] gnd23/24 vdd23/24 uto_txadr[1] uto_txadr[0] p[17] p[16] p[15] p[14] p[13] p[12] p[11] p[10] p[9] p[8] p[7] gnd21 vdd21 p[6] p[5] p[4] p[3] p[2] p[1] p[0 ] data[31] data[30] data[29] data[28] data[27] data[26] vdd19 gnd19 data[25] data[24] data[23] data[22] 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 uto_rxd[1] uto_rxd[2] uto_rxd[3] uto_rxd[4] gnd27 vdd27 uto_rxd[5] uto_rxd[6] uto_rxd[7] uto_rxsoc uto_rxenb uto_rxclav uto_clk scl sda uclk uarxd uatxd nuadtr vdd29/35 gnd29/35 nuadsr mdc mdio col rxd[0] rxd[1] rxd[2] rxd[3] rx_dv rx_clk rx_err tx_clk txd[0] vdd31/32 gnd31/32 txd[1] txd[2] txd[3] tx_en tx_err crs usb_dp usb_dn spimiso spimosi spiclk vdd33 gnd33 tmode fmode clksel 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 figure 3 S5N8947 pin configuration notes under - bar in the figure 2 means the muxing pins.
electronics S5N8947 (mcu for dsl) page : 13 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 4.2. logic symbol diagram 4.2.1 mode 1 (1 sar + 1 mii + 1 usb) pcmcia xclk_i nreset osc_xin osc_xo system memory & external interface mii filter_s filter_u mclko b0size[1:0] jtag ntrst tms tck tdi tdo extmreq extmack ndtack noe necs[3:0] nrcs[3:0] nras[3:0] ncas[3:0] ndwe nwbe[3:0] addr[21:0] data[31:0] gpio utopia l 1/2 uto_txadr[1:0] uto_txd[7:0] uto_txsoc uto_txenb uto_txclav uto_rxadr[1:0] uto_rxd[7:0] uto_rxsoc uto_rxenb uto_rxclav uto_clk iicc scl sda uart uclk uarxd uatxd nuadtr nuadsr mdc mdio col rxd[3:0] rx_dv rx_clk rx_err tx_clk txd[3:0] tx_en tx_err crs usb_dp usb_dn usb spimiso spimosi spi spiclk tmode fmode clksel bigend mode S5N8947 ( fmode = 0 ) external i/f & gpio signals p[17:0]
S5N8947 (mcu for dsl) electronics dsl group page : 14 october 26 , 2001 rev 1.8 samsung electronics figure 4 S5N8947 logic symbol diagram (mode 1) 4.2.2 mode 2 (1 sar + 2 mii + 1 usb) xclk_i nreset osc_xin osc_xo system memory & external interface mii filter_s filter_u mclko b0size[1:0] jtag ntrst tms tck tdi tdo extmreq extmack ndtack noe necs[2:0] nrcs[3:0] nras[3:0] ncas[3:0] ndwe nwbe[3:0] addr[21:0] data[31:0] gpio p[4:0] utopia l 1/2 uto_txadr[1:0] uto_txd[7:0] uto_txsoc uto_txenb uto_txclav uto_rxadr[1:0] uto_rxd[7:0] uto_rxsoc uto_rxenb uto_rxclav uto_clk iicc scl sda uart uarxd uatxd nuadtr nuadsr mdc mdio col rxd[3:0] rx_dv rx_clk rx_err tx_clk txd[3:0] tx_en tx_err crs usb_dp usb_dn usb spimiso spimosi spi spiclk tmode fmode clksel bigend mode S5N8947 ( fmode = 1 ) mii mdc mdio col rxd[3:0] rx_dv rx_clk rx_err tx_clk txd[3:0] tx_en tx_err crs figure 5 S5N8947 logic symbol diagram (mode 2)
electronics S5N8947 (mcu for dsl) page : 15 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 4.3 pin descriptions with the pin number and pad type pin no pin name i /o type pad type descriptions 1 b0size[0] i phic 2 b0size[1] i phic *3 unconnection i phic muxing with srx_clk 4 nreset i phtis 5 osc_xin i phsoscm2 6 osc_xo o phsoscm2 7 gnd36 p vss3o 8 xclk_i i phic 9 gnd1 p vbb1_abb 10 filter_s o poar5 0_abb 11 filter_u o poar50_abb 12 vdd3/4 p vdd1t_abb 1.8v 13 gnd3/4 p vss1t_abb 14 extmreq i phic 15 extmack o phob1 16 bigend i phicd 17 mclko o phob4 18 gnd5 p vss3p *19 unconnection b phbcut4 muxing with smdio 20 vdd5 p vdd3p 3.3v 21 ntrst i phicu 22 tms i phicu 23 tck i phic 24 tdi i phicu 25 tdo o phtot2 26 ndack i phicu 27 noe o phot4 28 necs[0] o phot4 29 necs[1] o phot4 *30 necs[2] o phot4 muxing with stxd[3] *31 necs[3] o phot4 muxing with smdc 32 nrcs[0] o ph ot4 33 nrcs[1] o phot4 34 nrcs[2] o phot4 35 vdd7/8 p vdd3o 3.3v 36 gnd7/8 p vss3o 37 nrcs[3] o phot4 not pcmcia select 38 nras[0] o phot4 39 nras[1] o phot4 40 nras[2] o phot4 41 nras[3] o phot4 42 ncas[0] o phot4 43 ncas[1] o phot4 44 ncas[2] o phot4 45 ncas[3] o phot4 46 ndwe o phot4
S5N8947 (mcu for dsl) electronics dsl group page : 16 october 26 , 2001 rev 1.8 samsung electronics 47 nwbe[0] o phot4 48 vdd9 p vdd1ih 1.8v 49 gnd9 p vss3i 50 nwbe[1] o phot4 nwbe[1]/iord(pcmcia only) 51 nwbe[2] o phot4 nwbe[2]/iowr(pcmcia only) 52 nwbe[3] o phot4 53 - 56 addr[0:3] o pho t4 57 gnd11 p vss3i 58 vdd11 p vdd1ih 1.8v 59 - 71 addr[4:16] o phot4 72 vdd13/34 p vdd3o 3.3v 73 gnd13/34 p vss3o 74 - 78 addr[17:21] o phot4 79 - 86 data[0:7] b phbcut4 87 vdd15/16 p vdd3o 3.3v 88 gnd15/16 p vss3o 89 - 99 data[8:18] b phbcut4 100 vdd17 p vdd1ih 1.8v 101 gnd17 p vss3i 102 - 108 data[19 - 25] b phbcut4 109 gnd19 p vss3 i 110 vdd19 p vdd1ih 1.8v 111 - 116 data[26 - 31] b phbcut4 117 - 120 p[0 :3] b phbcut4 *121 p[4] b phbcut4 muxing with stxd[0] *122 p[5] b phbcut4 muxing with st xd[1] *123 p[6] b phbcut4 muxing with stxd[2] 124 vdd21 p vdd3p 3.3v 125 gnd21 p vss3p *126 p[7] b phbcut4 muxing with srx_dv 127 - 129 p[8 - 10] b phbcut4 *130 p[11 ] b phbcut4 muxing with scrs *131 p[12] b phbcut4 muxing with srxd[0] *132 p[13] b ph bcut4 muxing with srxd[1] *133 p[14] b phbcut4 muxing with srxd[2] *134 p[15] b phbcut4 muxing with srxd[3] 135 p[16] b phbcut4 *136 p[17] b phbcut4 muxing with srx_err 137 - 138 uto_txadr[0:1] o phob4 139 vdd23/24 p vdd3o 3.3v 140 gnd23/24 p vss3o 141 - 145 uto_txd[0:4] o phob4 *146 uto_txd[5] o phob4 muxing with bist_errob *147 uto_txd[6] o phob4 muxing with bist_diag *148 uto_txd[7] o phob4 muxing with bist_done 149 uto_txsoc o phob4 150 uto_txenb o phob4 151 uto_txclav i phtis 152 vdd2 5 p vdd1ih 1.8v
electronics S5N8947 (mcu for dsl) page : 17 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 153 gnd25 p vss3i 154 - 155 utop_rxadr[0:1] o phob4 *156 uto_rxd[0] i phtis muxing with bist_on *157 uto_rxd[1] i phtis muxing with bist_mode *158 uto_rxd[2] i phtis muxing with bist_memsel[0] *159 uto_rxd[3] i phtis muxing with bist_ memsel[1] *160 uto_rxd[4] i phtis muxing with bist_memsel[2] 161 gnd27 p vss3i 162 vdd27 p vdd1ih 1.8v *163 uto_rxd[5] i phtis muxing with bist_memsel[3] 164 - 165 uto_rxd[6:7] i phtis 166 uto_rxsoc i phtis 167 uto_rxenb o phob4 168 uto_rxclav i phtis 169 uto_clk o phob4 170 scl b phbcud4 171 sda b phbcud4 *172 uclk i phic muxing with stx_clk 173 uarxd i phic 174 uatxd o phob4 175 nuadtr i phic 176 vdd29/35 p vdd3o 3.3v 177 gnd29/35 p vss3o 178 nuadsr o phob4 179 mdc o phob4 180 mdio b phbcut4 181 col i phic 7 - wire pin *182 rxd[0] i phic muxing with test_mode[0] , 7 - wire pin *183 rxd[1] i phic muxing with test_mode[1] *184 rxd[2] i phic muxing with test_mode[2] *185 rxd[3] i phic muxing with test_mode[3] 186 rx_dv i phic 187 rx_clk i phic 7 - wire pin 188 rx_err i phic 189 tx_clk i phic 7 - wire pin 190 txd[0] o phob4 7 - wire pin 191 vdd31/32 p vdd3o 3.3v 192 gnd31/32 p vss3o 193 - 195 txd[1:3] o phob4 196 tx_en o phob4 7 - wire pin 197 tx_err o phob4 198 crs i phic 7 - wire pin 199 usb_dp b pbusbfs 200 usb_dn b pbusbfs *201 spimiso i phic muxing with scol *202 spimosi o phob4 muxing with stx_en *203 spiclk o phob4 muxing with stx_err 204 vdd33 p vdd1ih 1.8v 205 gnd33 p vss3i
S5N8947 (mcu for dsl) electronics dsl group page : 18 october 26 , 2001 rev 1.8 samsung electronics 206 tmode i phic 207 fmode i p hic 208 clksel i phic 4.4 pad descriptions 4.4.1 input pads pad types descriptions phic / phics / phicu 3.3v interface lvcmos level input buffer phis / phisd / phisu 3.3v interface lvcmos schmitt trigger level input buffer phtis / phtisd / phtisu 5v tolera nt for 3.3v interface cmos schmit trigger level input buffer 4.4.2 output pads pad types descriptions phob (1/4/8) 3.3v lvcmos normal output buffers phot (1/4/8) 3.3v lvcmos tri - state output buffers 4.4.3 bi - direction pads pad types descriptions phbcut4 ( ph batyz ) 3.3v tri - state bi - direction buffers phbcud4 ( phbaudyz ) 3.3v open - drain bi - directional buffers with pull - up 4.4.4 power pads pad characteristics pad types supply voltage descriptions 1.8v interface digital i/o vdd1i 1.8v 1.8v internal vdd3p 3.3v 3.3v pre - driver 3.3v interface digital i/o vdd3o 3.3v 3.3v output - driver 1.8v interface digital i/o vss1i internal gnd for 1.8v interface i/o vss3p pre - driver gnd for 3.3v interface i/o 3.3v interface digital i/o vss3o output - driver gnd for 3.3v interfa ce i/o 1.8v interface analog i/o vdd1t_abb 1.8v 1.8v total vss1t_abb total gnd for 1.8v interface i/o 1.8v interface analog i/o vss1_abb bulk - bias gnd for 1.8v interface i/o
electronics S5N8947 (mcu for dsl) page : 19 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 5. o peration d escription 5.1. cpu core overview the S5N8947 cpu core is the arm7td mi processor, a general purpose, 32 - bit microprocessor developed by advanced risc machines, ltd. (arm). the core's architecture is based on reduced instruction set computer (risc) principles. the risc architecture makes the instruction set and its related decoding mechanisms simpler and more efficient than those with microprogrammed complex instruction set computer (cisc) systems. the resulting benefit is high instruction throughput and impressive real - time interrupt response. pipelining is also employed so that all components of the processing and memory systems can operate continuously. the arm7tdmi has a 32 - bit address bus. an important feature of the arm7tdmi processor, and one which differentiates it from the arm7 processor, is a unique architectural st rategy called thumb. the thumb strategy is an extension of the basic arm architecture and consists of 36 instruction formats. these formats are based on the standard 32 - bit arm instruction set, but have been re - coded using 16 - bit wide opcodes. address register address incrementer register bank multiplier barrel shifter 32-bit alu write data register instruction decoder and logic controll instruction pipeline and read data register figure 6 arm7tdmi core block diagram
S5N8947 (mcu for dsl) electronics dsl group page : 20 october 26 , 2001 rev 1.8 samsung electronics because thumb instructions are one - half the bit width of normal arm instructions, they produce very high - density code. when a thumb instruction is executed, its 16 - bit op code is decoded by the processor into its equivalent instruction in the standard arm instruction set. the arm core then processes the 16 - bit instruction as it would a normal 32 - bit instruction. in other words, the t humb architecture gives 16 - bit systems a way to access the 32 - bit performance of the arm core without incurring the full overhead of 32 - bit processing. because the arm7tdmi core can execute both standard 32 - bit arm instructions and 16 - bit t humb instructions, it lets you mix routines of t humb inst ructions and arm code in the same address space. in this way, you can adjust code size and performance, routine by routine, to find the best programming solution for a specific application. 5.2. instruction set the S5N8947 instruction set is divided into two subsets: a standard 32 - bit arm instruction set and a 16 - bit thumb instruction set . the 32 - bit arm instruction set is comprised of thirteen basic instruction types which can be divided into four broad classes: l four types of branch instructions which contro l program execution flow, instruction privilege levels, and switching between arm code and thumb code. l three types of data processing instructions which use the on - chip alu, barrel shifter, and multiplier to perform high - speed data operations in a bank of 31 registers (all with 32 - bit register widths). l three types of load and store instructions which control data transfer between memory locations and the registers. one type is optimized for flexible addressing, another for rapid context switching, and the t hird for swapping data. l three types of co - processor instructions which are dedicated to controlling external co - processors. these instructions extend the off - chip functionality of the instruction set in an open and uniform way. notes : all 32 - bit arm instr uctions can be executed conditionally. the 16 - bit thumb instruction set contains 36 instruction formats drawn from the standard 32 - bit arm instruction set. the thumb instructions can be divided into four functional groups: l four branch instructions. l twelve data processing instructions, which are a subset of the standard arm data processing instructions. l eight load and store register instructions. l four load and store multiple instructions. notes : each 16 - bit thumb instruction has a corresponding 32 - bit arm instruction with the identical processing model. the 32 - bit arm instruction set and the 16 - bit thumb instruction sets are good targets for compilers of many different high - level languages. when assembly code is required for critical code segments, the arm programming technique is straightforward, unlike that of some risc processors which depend on sophisticated compiler technology to manage complicated instruction interdependencies. pipelining is employed so that all parts of the processor and memory syste ms can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
electronics S5N8947 (mcu for dsl) page : 21 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 5.3. o perating s tates from a programmer's point of view, the arm7tdmi core is always in one of two operating states. these states, which can be switched by software or by exception processing, are: l arm state (when executing 32 - bit, word - aligned, arm instructions), and l thumb state (when executing 16 - bit, half - word aligned thumb instructions). 5.4. o perating m odes the arm7tdmi core supports seven operating modes: l user mode: the normal program execution state l fiq (fast interrupt request) mode: for supporting a specific data transfer or channel process l irq (interrupt request) mode: for general purpose interrupt handling l supervisor mode: a protected mode for the operating system l abort mode: entered when a data or instruction pre - fetch is aborted l system mode: a privileged user mode for the operating system l undefined mode: entered when an undefined instruc tion is executed operating mode changes can be controlled by software, or they can be caused by external interrupts or exception processing. most application programs execute in user mode. privileged modes (that is, all modes other than user mode) are ent ered to service interrupts or exceptions, or to access protected resources. 5.5. r egisters the S5N8947 cpu core has a total of 37 registers: 31 general - purpose 32 - bit registers, and 6 status registers. not all of these registers are always available. which re gisters are available to the programmer at any given time depends on the current processor operating state and mode. notes : when the S5N8947 is operating in arm state, 16 general registers and one or two status registers can be accessed at any time. in pr ivileged mode, mode - specific banked registers are switched in. two register sets, or banks, can also be accessed, depending on the core's current state: the arm state register set and the thumb state register set: l the arm state register set contains 16 di rectly accessible registers: r0 - r15. all of these registers, except for r15, are for general - purpose use, and can hold either data or address values. an additional (seventeenth) register, the cpsr (current program status register), is used to store status information. l the thumb state register set is a subset of the arm state set. you can access eight general registers, r0 - r7, as well as the program counter (pc), a stack pointer register (sp), a link register (lr), and the cpsr. each privileged mode has a co rresponding banked stack pointer, link register, and saved process status register (spsr). the thumb state registers are related to the arm state registers as follows:
S5N8947 (mcu for dsl) electronics dsl group page : 22 october 26 , 2001 rev 1.8 samsung electronics l thumb state r0 - r7 registers and arm state r0 - r7 registers are identical l thumb state cps r and spsrs and arm state cpsr and spsrs are identical l thumb state sp, lr, and pc map directly to arm state registers r13, r14, and r15, respectively in thumb state, registers r8 - r15 are not part of the standard register set. however, you can access them for assembly language programming and use them for fast temporary storage, if necessary. 5.6. e xceptions an exception arises whenever the normal flow of program execution is interrupted. for example, when processing must be diverted to handle an interrupt fr om a peripheral. the processor's state just prior to handling the exception must be preserved so that the program flow can be resumed when the exception routine is completed. multiple exceptions may arise simultaneously. to process exceptions, the S5N8947 uses the banked core registers to save the current state. the old pc value and the cpsr contents are copied into the appropriate r14 (lr) and spsr register. the pc and mode bits in the cpsr are forced to a value which corresponds to the type of exception b eing processed. the S5N8947 core supports seven types of exceptions. each exception has a fixed priority and a corresponding privileged processor mode, as shown in following table exception mode on entry priority reset supervisor mode 1 (highest) data a bort abort mode 2 fiq fiq mode 3 irq irq mode 4 prefetch abort abort mode 5 undefined instruction undefined mode 6 swi supervisor mode 6 (lowest) table 2 S5N8947 cpu exceptions
electronics S5N8947 (mcu for dsl) page : 23 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 6. h ardware s tructure 6.1. system manager 6.1.3. overview the S5N8947 microcontroller ? s system manager has the following functions. l arbitrates system bus access requests from several master blocks, based on fixed priorities. l provides the required memory control signals for external memory accesses. for example , if a master block such as the dma controller or the cpu generates an address, which corresponds to a dram bank, the system manager ? s dram controller generates the required normal/edo or sdram access signals. the interface signals for normal/edo or sdram can be switched by syscfg[31]. l provides the required signals for bus traffic between the S5N8947 and rom/sram and the external i/o banks. l compensates for differences in bus width for data transfer between the external memory bus and the internal data bus. l supports both little and big endian for external memory or i/o devices. internal registers, however, operate under big - endian mode. l supports both motorola mode and intel mode for external i/o devices l supports an external bus master with bus request(extmre q) and bus acknowledge(extmack) l supports pcmcia ? memory and i/o ? master mode 6.1.4. system manager registers to control external memory operations, the system manager uses a dedicated set of special registers. by programming the values in the system manager s pecial registers, you can specify such things as: l memory type l external data access cycle l external memory and i/o device access cycle l memory bank locations l size of each memory bank to be used for arbitrary address spacing
S5N8947 (mcu for dsl) electronics dsl group page : 24 october 26 , 2001 rev 1.8 samsung electronics the system manager uses special r egister setting to control the generation and processing of the control signals, addresses, and data that are required by external devices in a standard system configuration. special registers are also used to control access to rom/sram/flash banks, a pcmc ia interface, up to four dram banks and four external i/o banks, and a special register mapping area. the address resolution for each memory bank base pointer is 64 kbytes (16 bits). the base address pointer is 10 bits. this gives a total addressable memor y bank space of 16 m words. 16k words-4m words (32 bits) addr [21:0] 4k words (fixed for all i/o banks) continuous 16k word space for 4 external i/o banks 16k words (fixed) 0x3ffffff 16m words (16m x 32 bits) sa [25:0] 0x0000000 note: you can define banks anywhere within the 64-mbyte address space. pcmcia bank rom/sram/flash bank 2 rom/sram/flash bank 1 rom/sram/flash bank 0 reserved special register bank reserved external i/o bank 3 external i/o bank 2 external i/o bank 1 external i/o bank 0 dram/sdram bank 3 dram/sdram bank 2 dram/sdram bank 1 dram/sdram bank 0 64k bytes-4m bytes (16 bits) addr [21:0] figure 7 S5N8947 system memory map
electronics S5N8947 (mcu for dsl) page : 25 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 6.1.5. system memory map followings are several important features to note about the S5N8947 system memory map: l the size and locatio n of each memory bank is determined by the register settings for ? current bank base pointer ? and ? current bank end pointer ? . you can use this base/next bank pointer concept to set up a consecutive memory map. to do this, you set the base pointer of the ? ne xt bank ? to the same address as the next pointer of the ? current bank ? . please note that when setting the bank control registers, the address boundaries of consecutive banks must not overlap. this can be applied even if one or more banks are disabled. l four external i/o banks are defined in a continuous address space. a programmer can only set the base pointer for external i/o bank 0. the start address of external i/o bank 1 is then calculated as the external i/o bank 0 start address +16 k. similarly , the st art address for external i/o bank 2 is the external i/o bank 0 start address + 32 k, and the start address for external i/o bank 3 is the external i/o bank 0 start address + 48 k. therefore, the total consecutive addressable space of the four external bank s is defined as the start address of external i/o bank 0 + 64 k bytes. l within the addressable space, the start address of each i/o bank is not fixed. you can use bank control registers to assign a specific bank start address by setting the bank ? s base poin ter. the address resolution is 64 k bytes. the bank ? s start address is defined as ? base pointer << 16 ? and the bank ? s end address (except for external i/o banks) is ? next pointer << 16 ? 1 ? . after a power - on or system reset, all bank address pointer regis ters are initialized to their default values. in this means that a system reset automatically defines rom bank 0 as a 32 - mbyte space with a start address of zero. this means that, except for rom bank 0, all banks are undefined following a system startup. t he reset values for the next pointer and base pointer of rom bank 0 are 0x200 and 0x000, respectively. this means that a system reset automatically defines rom bank 0 as a 32 - mbyte space with a start address of zero. this initial definition of rom bank 0 l ets the system power - on or reset operation pass control to the user - supplied boot code that is stored in external rom. (this code is located at address 0 in the system memory map.) when the boot code (i.e. rom program) executes, it performs various system initialization tasks and reconfigures the system memory map according to the application ? s actual external memory and device configuration. the initial system memory map following system startup is shown in following:
S5N8947 (mcu for dsl) electronics dsl group page : 26 october 26 , 2001 rev 1.8 samsung electronics rom/sram/flash bank 0 area (accessible) undefined area special function registers 4 m address[21:0] rom/sram/flash bank 0 area (accessible) 32 m 64 m bytes sa[25:0] 0x0000000 0x2000000 0x3ff0000 0x3ffffff figur e 8 initial system memory map (after reset)
electronics S5N8947 (mcu for dsl) page : 27 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 6.2. instruction / data cache the S5N8947 cpu has a unified internal 8 - kbyte instruction/data cache. the cache is configured using two - way, set - associative addressing. the replaceme nt algorithm is pseudo - lru (least recently used). the cache line size is four words (16 bytes). when a miss occurs, four words must be fetched consecutively from external memory. typically, risc processors take advantage of unified instruction/data caches to improve performance. switch cs set 1 tag set 0 tag 14 2 tag ram (32-bit) set 1 icache line = 4 instruction/data (256-bit) set 0 icache line = 4 instruction/data (256-bit) decoder 8-bit 2-bit height = 256 8-bit height = 256 32 2 (set 0 hit) (set 1 hit) 14 enable non-cacheable control {[28], [24:23]} == 100: set 0 direct access 101: set 1 direct access 110: tag direct access 14 2 32 32 instr3 instr2 instr1 instr0 32-bit instr3 instr2 instr1 instr0 32-bit 8-bit 31 27 28 tag address (14-bit) 25 0 30 29 26 12 11 4 3 2 1 0 13 15 28 30 31 figure 9 memory configuration for 8 - kbyte cache
S5N8947 (mcu for dsl) electronics dsl group page : 28 october 26 , 2001 rev 1.8 samsung electronics 6.3. i 2 c bus controller the S5N8947 ? s internal ic bus (i 2 c - bus) controller has the following important features: l it requires only two bus lines, a serial data line (sda) and a serial clock line (scl). when the i 2 c - bus is free, both lines are high level. l each device that is connected to the bus is software - addressable by a unique address. slave relationships on the bus are const ant. the bus master can be either a master - transmitter or a master - receiver. the i 2 c bus controller supports only single master mode. l it supports 8 - bit, bi - directional, serial data transfers. l the number of ics that you can connect to the same i 2 c - bus is li mited only by the maximum bus capacitance of 400 pf. following figure shows a block diagram of the S5N8947 ? s i 2 c - bus controller. data control scl control serial clock prescaler control status register (iiccon) 0 busy cond1 cond0 ack lrb ien prescaler register (iicps) system clock (fmclk) 16 scl sda bf shift buffer register (iicbuf) figure 10 i 2 c - bus block diagram
electronics S5N8947 (mcu for dsl) page : 29 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 6.4. ethernet controller the s5n8 947 has 2 - channel ethernet controller which operates at either 100/ 10 - mbits per second in half - duplex or full - duplex mode. in half - duplex mode, the controller supports the ieee 802.3 carrier sense multiple access with collision detection (csma/cd) protocol . in full - duplex mode, it supports the ieee 802.3 mac control layer, including the pause operation for flow control. 6.4.1. block diagram s y s t e m b u s b d i m i i / 10 m b p s 7 - w i r e bdma tx buffer controller bdma tx buffer (64 words) bus arbiter/ controller bdma rx buffer (64 words) bdma rx buffer controller cam contents memory (32-words) bdma control and status register max tx buffer (80 bytes) max tx buffer controller mac max rx buffer (16 bytes) max rx buffer controller address cam interface and comparator flow controller crc checker mac control and status register station manager bdma+sbus i/f 32 32 32 32 32 32 8 8 figure 11 ethernet controller block diagram 6.4.2. features and benef its the most important features and benefits of the S5N8947 ethernet controller are as follows: l cost - effective connection to an external repeater interface controller( ric ) /ethernet backbone l buffered dma (bdma) engine using burst mode l bdma tx/rx buffers ( 256 bytes/256 bytes) l mac tx/rx fifos (80 bytes/16 bytes) to support re - transmit after collision without dma request and to handle dma latency l data alignment logic
S5N8947 (mcu for dsl) electronics dsl group page : 30 october 26 , 2001 rev 1.8 samsung electronics l support s for old and new media (compatible with existing 10 - mbit/s networks) l full ieee 802.3 compatibility for existing applications l provides a standard media independent interface (mii) l provides an external 7 - wire interface , also. l station management (sta) signaling for external physical layer configuration and link negotiation l on - chip cam (21 add resses) l full - duplex mode for doubled bandwidth l pause operation hardware support for full - duplex flow control l long packet mode for specialized environments l short packet mode for fast testing l pad generation for ease of processing and reduced processing time l support for old and new media : compatible with existing 100/ 10mbit/s networks. l full ieee 802.3 compatibility : compatible with existing hardware and software. l standard csma/cd,full duplex capability at 100/ 10 mbit/s : increase in data throughput performan ce.
electronics S5N8947 (mcu for dsl) page : 31 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 6.5. sar and utopia interface the S5N8947 provides atm layer segmentation and reassembly (sar) function over a 8bit utopia interface. the S5N8947 delivers an integrated solution for performing the sar tasks required to communicate over an atm network. th e device translates packet - based data into 53 - byte atm cells that are asynchronously mapped into various physical media. the S5N8947 can be effectively applied for equipment requiring an interface between packet - based data and atm - based networks. 6.5.1. block di agram reassembler aal5, 3/ 4, 0 segmentor aal5, 3/4, 0 scheduler (cbr,ubr,rt-vbr,nrt-vbr) registers connection memory (internal and/or external) utopia and fifos system i/f and fifos figure 12 sar function block diagram
S5N8947 (mcu for dsl) electronics dsl group page : 32 october 26 , 2001 rev 1.8 samsung electronics 6.5.2. features and benefits l supports cbr, ubr, rt - vbr and nrt - vbr traffic with rates set on a per - vc or per - vp basis. l supports aal0 (raw cells) and aal5 se gmentation and reassembly. l segments and reassembles data up to about 70m bps via utopia interface. l generates and verifies crc - 10 for oam cells and aal3/4 cells. l supports concurrent oam cells and aal5 cells on each active connection. l supports simultaneous s egmentation and reassembly of up to 32 connections with internal memory and up to 4k connections with external memory. l on chip 8k bytes sram for internal connection memory. l supports contents addressable memory (cam) for channel mapping (up to 32 connection s). l supports packet sizes up to 64k bytes. l supports scatter and gather packet capability for large packets l start of packet offset available for ease of implementing bridging and routing between different protocols. l provides glue - less utopia level 2 interfa ce (up to 3 phys). l supports big and little endian.
electronics S5N8947 (mcu for dsl) page : 33 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 6.6. usb controller the universal serial bus (usb) is an industry standard bus architecture for computer peripheral attachment. the usb provides a single interface for easy, plug - and - play, hot - plug attachmen t of peripherals such as keyboard, mouse, speakers, printers, scanners, and communication devices. the usb allows simultaneous use of many different peripherals with a combined transfer rate of up to 12 mbit/s. the s5n89 47 controller includes a highly flex ible integrated usb peripheral controller that lets designers implement a variety of microcontroller - based usb peripheral devices for telephony, audio, or other high - end applications. the S5N8947 controller is intended for usb peripherals that use the ful l - speed signalling rate of 12 mbit/s. the usb low - speed rate (1.5 mbit/s) is not supported. an integrated usb transceiver is provided to minimize system device count and cost. the usb peripheral controller?s features meet or exceed all of the usb device cl ass resource requirements defined by the usb specification version 1.0 and 1.1. consult the usb specification for details about overall usb system design. the integrated usb peripheral controller provides a very efficient and easy - to - use interface, so that device software (or firmware) does not incur the overhead of managing low - level usb protocol requirements. the usb peripheral controller hardware implements a number of usb standard commands directly; the rest can be implemented in device software. in ad dition, the usb peripheral controller provides a high degree of flexibility to help designers accommodate vendor - or device - class - specific commands, as well as any new features that might be added in future usb specifications. specialized hardware is provi ded to support bulk data transfers. using the microcontroller?s dma features, large size of bulk transfers from an off - chip peripheral, can be automatically synchronized to the usb data rate with little or no cpu overhead. robust error detection and manage ment features are provided so the device software can manage transfers in any number of ways as required by the application. the usb suspend/resume, reset, and remote wake up features are also supported. 6.6.1. block diagram serial interface engine (sie) serial interface unit (sie) endpoint 1 16 out fifo endpoint 0 fifo endpoint 2 16 in fifo mcu address decoder host mcu / dma interface endpoint 3 64 out fifo endpoint 4 64 in fifo x 2 x 2 figure 13 usb module block diagram
S5N8947 (mcu for dsl) electronics dsl group page : 34 october 26 , 2001 rev 1.8 samsung electronics 6.7. dma controller the S5N8947 has a two - channel general dma controller, called the gdma. the two - channel gdma performs the following data transfers without cpu intervention: l memory - to - memory (memory to/from memory) l uart - to - memory (serial port to/from memory) l spi - to - memory (spi port to/from memory) the on - chip gdma can be started by software and/or by an external dma request (nxdreq). software can also be used to restart a gdma operation after it has been stopped. the cpu can recognize when a gdma operation has been completed by software polling and/or when it receives an appropriate internally generated gdma interrupt. the S5N8947 gdma controller can increment or decrement source or destination addres ses and conduct 8 - bit (byte), 16 - bit (half - word), or 32 - bit (word) data transfers.
electronics S5N8947 (mcu for dsl) page : 35 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential system bus gdma channel 0 ndreq ndack gdma channel 1 ndreq ndack port 14 data gdma0 iopcon [27:26] nxdack 0 iopcon [29:28] nxdack 1 port 15 data gdma1 mode selection mode selection nxdreq 1 spi (to memory) uart nxdreq 0 spi (from memory) figure 14 gdma controller block diagram 6.8. uart the S5N8947 universal asynchronous receiver/transmitte r (uart) unit provides an asynchronous serial i/o (sio) port. this can operate in interrupt - based or dma - based mode. that is, the uart can generate internal interrupts or dma requests to transfer data between the cpu and the serial i/o port. the most important features of the S5N8947 uart include: l programmable baud rates l infra - red (ir) transmit/receive l insertion of one or two stop bits per frame l selectable 5 - bit, 6 - bit, 7 - bit, or 8 - bit data transfers l parity checking this unit has a baud rate gene rator, transmitter, receiver, and a control unit, as shown in next figure . the baud - rate generator can be driven by the internal system clock, mclk. the transmitter and receiver block use this baud rate clock and have independent data buffer registers and data shifters. transmit data is written first to the transmit buffer register. from there, it is copied to the transmit shifter and then shifted out by the transmit data pin, uatxdn. receive data is shifted in by the receive data pin, uarxdn. it is then co pied from the shifter to the receive buffer register when one data byte has been received. this unit provide s software controls for mode selection, and for status and interrupt generation.
S5N8947 (mcu for dsl) electronics dsl group page : 36 october 26 , 2001 rev 1.8 samsung electronics transmit buffer register (utxbufn) transmit shift register baud rate generator baud rate divisor (utbufn) system bus receive buffer register (urxbufn) receive shift register line control register (ulconn) uart status register (ustatn) uart control register (uconn) ir rx decoder uarxdn nuadtrn nuadsrn ir rx decoder 0 1 0 1 uatxdn figure 15 uart block diagram 6.9. timers the S5N8947 has three 32 - bit timers. these timers can operate in interval mode or in toggle mode. the output signals are tout0 and tout1, respectively. you enable or disable the timers by setting control bits in the timer mo de register, t mod . an interrupt request is generated whenever a timer count - out (down count) occurs. watchdog timer is also implemented in the S5N8947. the following guidelines apply to watchdog timer functions : ? when a watchdog timer is enabled, it loads a data value to its count register and begins decrementing the count register value by the system clock . ? if the reset from the w atchdog timer (wdreset) reaches to zero , the watchdog will start its reset s equence. the reset value is then reloaded and the w atchdog timer is disabled . ? the wdreset performs the same function as the external reset (system reset) to each block .
electronics S5N8947 (mcu for dsl) page : 37 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential f mclk 32-bit timer count register (tcntn) [down counter] 32-bit timer data register (tdatan) pulse generator tmod.ten tmod.tmdn tmod.tclrn pnd intpnd and intmsk interrupt request port 16, port 17 data out iopcon.toenn auto re-load toutn figure 16 32 - bit timer block diagram 6.10. i/o ports the S5N8947 has 18 programmable i/o ports. you can configure each i/o port to input mode, output mode, or special function mode. to do this, you write the appropriate settings to the iopmod , iopcon0 and iopcon 1 registers. user can set filtering for the input ports using iopcon 0/1 register. port[0] can be used as nce1 for pcmcia interface or spiclk, port[1] as nce2 for pcmcia interface or spimosi, port[2] as niois16 for pcmcia interface or spimiso, port[3] as nale for pcmcia interface, port[4] as rw(external data transceiv er direction) for pcmcia interface, or port[7:5] as xintreq[2:0] depending on the settings in iopcon0 register . and port[11:8] can be used as xintreq[ 6:3 ], port[13:12] as nxdreq[1:0], port[15:14] as nxdack[1:0], port[16] as tout0, or port[17] as tout1 depe nding on the settings in iopcon 1 register.
S5N8947 (mcu for dsl) electronics dsl group page : 38 october 26 , 2001 rev 1.8 samsung electronics system bus output latch input latch active on/off & edge detection iopdata (read) interrupt or dma request iopcon filter on/off iopcon iopdata (write) alternate functions iopcon v dd iopmod port0/nce1/spiclk port1/nce2/spimosi port2/niois16/ spimiso port3/nale port4/rw port5/xintreq0 port6/xintreq1 ... port11/xintreq6 port12/nxdreq0 port13/nxdreq1 port14/nxdack0 port15/nxdack1 port16/tout0 port17/tout1 figure 17 i/o port function diagram 6.11. interrupt controller the S5N8947 interrupt controller has a total of 23 interrupt sources. int errupt requests can be generated by internal function blocks and external pins. the arm7tdmi core recongnizes two kinds of interrupts: a normal interrupt request (irq), and a fast interrupt request (fiq). therefore all S5N8947 interrupts can be categorized as either irq or fiq. the S5N8947 interrupt controller has an interrupt pending bit for each interrupt source. four special registers are used to control interrupt generation and handling: l interrupt priority registers. the index number of each interrupt source is written to the pre - defined interrupt priority register field to obtain that priority. the interrupt priorities are pre - defined from 0 to 22 . l interrupt mode register. defines the interrupt mode, irq or fiq, for each interrupt source. l interrupt pen ding register. indicates that an interrupt request is pending. if the pending bit is set, the interrupt pending status is maintained until the cpu clears it by writing a "1" to the appropriate pending register. when the pending bit is set, the interrupt se rvice routine starts whenever the interrupt mask register is "0". the service routine must clear the pending condition by writing a "1" to the appropriate pending bit. this avoids the possibility of continuous interrupt requests from the same interrupt pen ding bit.
electronics S5N8947 (mcu for dsl) page : 39 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential l interrupt mask register. indicates that the current interrupt has been disabled if the corresponding mask bit is "1". if an interrupt mask bit is "0" the interrupt will be serviced normally. if the global mask bit (bit 23 ) is set to "1", no inter rupts are serviced. however, the source's pending bit is set if the interrupt is generated. when the global mask bit has been set to "0", the interrupt is serviced. index values interrupt sources [ 22 ] spi interrupt [ 21 ] i 2 c - bus interrupt [ 20 ] ethernet controller 1 rx interrupt [ 19 ] ethernet controller 1 tx interrupt [ 18 ] ethernet controller 0 rx interrupt [ 17 ] ethernet controller 0 tx interrupt [ 16 ] sar tx/rx done interrupt [ 15 ] sar tx/rx error interrupt [ 14 ] usb interrupt [ 13 ] gdma channel 1 in terrupt [ 12 ] gdma channel 0 interrupt [ 11 ] timer 2 interrupt [ 10 ] timer 1 interrupt [ 9 ] timer 0 interrupt [ 8 ] uart receive and error interrupt [ 7 ] uart transmit interrupt [ 6 ] external interrupt 6 [ 5 ] external interrupt 5 [ 4 ] external interrupt 4 [ 3 ] external interrupt 3 [2] external interrupt 2 [1] external interrupt 1 [0] external interrupt 0 table 3 S5N8947 interrupt sources 6.12. spi the S5N8947 provides a serial peripheral interface (spi), which is used for register a ccess of other devices, eeprom and a/d converter. the S5N8947 spi is full duplex, synchrounous channel and it consists of four signal, receive serial data, transmit serial data, clock and select. inner baud rate generator create spi clock and spi signals a re synchronized with this clock. spi can be operated with the help of gdma. so multiple characters can be transmitted and received without host intervention. otherwise, the host should transmit and receive individual character back - to - back with polling met hod. spi does not operate in slave mode and it also cannot be used for multimaster environment. it works with data characters from 4 to 32 bits long. clock phase and polarity can be configured.
S5N8947 (mcu for dsl) electronics dsl group page : 40 october 26 , 2001 rev 1.8 samsung electronics figure 18 i/o block diagram of spi (serial peripheral interface) transmit register receive register 32 bits shift register config register counter / control logic command register baud rate generator pins interface spisel spimiso spimosi spiclk gdma transmit register receive register 33 bits shift register config register counter / control logic command register baud rate generator pins interface mclk spimiso spimosi spiclk gdma apb bus gpio
electronics S5N8947 (mcu for dsl) page : 41 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 7. special function registers group registers offset r/w description reset/value syscfg 0x0000 r/w system configuration register 0x 23ff0000 pcmcon 0x3000 r/w pcmcia interface cont rol register 0x80000000 extacon0 0x3008 r/w external i/o timing register 1 0x00000000 extacon1 0x300c r/w external i/o timing register 2 0x00000000 extdbwth 0x3010 r/w data bus width for each memory bank 0x00000000 romcon0 0x3014 r/w rom/sram/flash bank 0 control register 0x20000060 romcon1 0x3018 r/w rom/sram/flash bank 1 control register 0x00000060 romcon2 0x301c r/w rom/sram/flash bank 2 control register 0x00000060 pcmoffset 0x3020 r/w pcmcia bank offset register 0x000000 0 dramcon0 0x3024 r/w dram bank 0 control register 0x00000000 dramcon1 0x3028 r/w dram bank 1 control register 0x00000000 dramcon2 0x302c r/w dram bank 2 control register 0x00000000 dramcon3 0x3030 r/w dram bank 3 control register 0x00000000 system manager refextcon 0x3034 r/w re fresh and external i/o control register 0x83fd0000 bdmatxcon 0x9000 r/w buffered dma receive control register 0x00000000 bdmarxcon 0x9004 r/w buffered dma transmit control register 0x00000000 bdmatxptr 0x9008 r/w transmit trame descri ptor start address 0x00000000 bdmarxptr 0x900c r/w receive frame descriptor start address 0x00000000 bdmarxlsz 0x9010 r/w receive frame maximum size undefined bdmastat 0x9014 r/w buffered dma status 0x00000000 cam 0x9100 - 0x917c r/ w cam content (32 words) undefined bdmatxbuf 0x9200 - 0x92fc r/w bdma tx buffer (64 words) for test mode addressing undefined ethernet 1 (bdma) bdmarxbuf 0x9800 - 0x99fc r/w bdma rx buffer (64 words) for test mode addressing undefined macon 0xa000 r/w ethernet mac control register 0x00000000 camcon 0xa004 r/w cam control register 0x00000000 mactxcon 0xa008 r/w mac transmit control register 0x00000000 mactxstat 0xa00c r/w mac transmit status register 0x00000000 macrxcon 0xa010 r/w mac receive control register 0x0000 0000 macrxstat 0xa014 r/w mac receive status register 0x00000000 stadata 0xa018 r/w station management data 0x00000000 stacon 0xa01c r/w station management control and address 0x00006000 camen 0xa028 r/w cam enable register 0x00000000 emisscnt 0x a03c r/w missed error count register 0x00000000 epzcnt 0xa040 r pause count register 0x00000000 ermpzcnt 0xa044 r remote pause count register 0x00000000 ethernet 1 (mac) etxstat 0x9040 r transmit control frame status 0x00000000 bdmatxcon 0xe000 r/w buffered dma receive control register 0x00000000 bdmarxcon 0x e 004 r/w buffered dma transmit control register 0x00000000 bdmatxptr 0xe008 r/w transmit trame descriptor start address 0x00000000 ethernet 2 (bdma) bdmarxptr 0xe00c r/w receive frame descriptor start addres s 0x00000000
S5N8947 (mcu for dsl) electronics dsl group page : 42 october 26 , 2001 rev 1.8 samsung electronics bdmarxlsz 0xe010 r/w receive frame maximum size undefined bdmastat 0xe014 r/w buffered dma status 0x00000000 cam 0xe100 - 0xe17c r/ w cam content (32 words) undefined bdmatxbuf 0xe200 - 0xe2fc r/w bdma tx buffer (64 words) for test mode a ddressing undefined bdmarxbuf 0xe800 - 0xe9fc r/w bdma rx buffer (64 words) for test mode addressing undefined macon 0xf800 r/w ethernet mac control register 0x00000000 camcon 0xf804 r/w cam control register 0x00000000 mactxcon 0xf808 r/w mac transmit control register 0x00000000 mactxstat 0xf80c r/w mac transmit status register 0x00000000 macrxcon 0xf810 r/w mac receive control register 0x00000000 macrxstat 0xf814 r/w mac receive status register 0x00000000 stadata 0xf818 r/w st ation management data 0x00000000 stacon 0xf81c r/w station management control and address 0x00006000 camen 0xf828 r/w cam enable register 0x00000000 emisscnt 0xf83c r/w missed error count register 0x00000000 epzcnt 0xf840 r pause count register 0x0 0000000 ermpzcnt 0xf844 r remote pause count register 0x00000000 ethernet 2 (mac) etxstat 0xe040 r transmit control frame status 0x00000000 fa 0x7000 r/w function address register 0x 00000000 pm 0x7004 r/w power/system management register 0x 00000000 int 0x7008 r/w interrupt register 0x 00000000 inte 0x700c r/w interrupt enable register 0x 0000041f fn 0x7010 r frame number register 0x00000000 e0sc 0x7014 r/w endpoint 0 status control register 0x00005080 e0sa 0x7018 r/w endpoint 0 dma start address register 0x 000000 0 0 e0xds 0x701c r/w endpoint 0 receive/transmit data size register 0x 000000 00 e0lds 0x7020 r/w endpoint 0 limit data size register 0x 008000 00 e1sc 0x7024 r/w endpoint 1 status control register 0x 000001 00 e1sa 0x7028 r/w endpoint 1 dma start address register 0x00000000 e1rds 0x702c r/w endpoint 1 transmit data size register 0x 000000 0 0 e1lds 0x7030 r/w endpoint 1 limit data size register 0x 008000 00 e2sc 0x7034 r/w endpoint 2 status control register 0x 0000508 0 e2sa 0x7038 r/w endpoint 2 dma start address register 0x00000000 e2tds 0x703c r/w endpoint 2 transmit data size register 0x00000000 e3sc 0x7040 r/w endpoint 3 status control register 0x 000000 0 4 e3sa 0x7044 r/w endpoint 3 dma start address register 0x 000000 00 e3rds 0x7048 r/ w endpoint 3 transmit data size register 0x 00000000 e3lds 0x704c r/w endpoint 3 limit data size register 0x 008000 00 e4sc 0x7050 r/w endpoint 4 status control register 0x 0000508 0 e4sa 0x7054 r/w endpoint 4 dma start address register 0x00000000 usb e4tds 0x7058 r/w endpoint 4 transmit data size register 0x00000000 sw_reset 0x8000 r/w software reset register 0x00000000 global_mode 0x 80 08 r/w global mode register 0x00000000 timeout_base 0x 80 0c r/w base multiple for receive packet timeout register 0 x00ff7fff tx_ready1 0x 80 10 r/w transmit ready first packet or subpacket address 0x00000000 tx_ready2 0x 80 14 r/w transmit ready last packet or subpacket address 0x00000000 tx_done_addr 0x 80 18 r/w transmit packet done queue base address register 0x0000 0000 tx_done_size 0x 80 1c r/w transmit packet done queue size register 0x00c00000 rx_pool0_addr 0x 80 20 r/w receive queue 0 base address register 0x00000000 rx_pool0_size 0x 80 24 r/w receive queue 0 size register 0x00c00000 sar rx_pool1_addr 0x 80 28 r/w re ceive queue 1 base address register 0x00000000
electronics S5N8947 (mcu for dsl) page : 43 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential rx_pool1_size 0x 80 2c r/w receive queue 1 size register 0x00c00000 rx_pool2_addr 0x 80 30 r/w receive queue 2 base address register 0x00000000 rx_pool2_size 0x 80 34 r/w receive queue 2 size register 0x00c000 00 rx_pool3_addr 0x 80 38 r/w receive queue 3 base address register 0x00000000 rx_pool3_size 0x 80 3c r/w receive queue 3 size register 0x00c00000 rx_done0_addr 0x 80 40 r/w receive packet done queue 0 base address register 0x00000000 rx_done0_size 0x 80 4 4 r/w receive packet done queue 0 size register 0x00c00000 rx_done1_addr 0x 80 48 r/w receive packet done queue 1 base address register 0x00000000 rx_done1_size 0x 80 4c r/w receive packet done queue 1 size register 0x00c00000 utopia_config 0x 80 50 r/w ut opia interface configuration register 0x00c00000 utopia_timeout 0x 80 54 r/w utopia interface timeout register 0xffffffff clock_ratio 0x 80 64 r/w ratio of sar clock freq touni interface speed 0x0000008e done_int_mask 0x 80 70 r/w interrupt mask for done i nterrupt register 0xffffffff err_int_mask 0x 80 74 r/w interrupt mask for error interrupt register 0xffffffff done_int_stat 0x 80 78 r/w interrupt status for done interrupt register 0x00000000 err_int_stat 0x 80 7c r/w interrupt status for error interrupt register 0x00000000 1/r_lookup_tbl 0x 80 80 r/w base address of 1/rate lookup table 0x00000000 vp_lookup_tbl 0x 80 84 r/w base address of vp lookup table 0x00200000 ubr_sch_tbl 0x 80 88 r/w base address and entry number of ubr schedule 0x0030007f cbr_sch _tbl 0x 80 8c r/w base address and entry number of cbr schedule 0x0038007f cell_buff 0x 80 90 r/w base address and entry number of cell buffer 0x0040000f sch_conn_tbl 0x 80 94 r/w base address and entry number of scheduler connection table 0x0050001f aal_c onn_tbl 0x 80 98 r/w base address and entry number of aal connection table 0x0060001f sar_conn_tbl 0x 80 9c r/w base address and entry number of sar connection table 0x00700000 cam_vpvc/cn 0x8100 - 0x81fc r/w cam vpci, vci and connection number register 0x00 000000 configuration 0x8200 r/w clock control and connection memory configuration register 0x000000 46 ext_cmbase 0x8204 r/w external connection memory base address register 0x00000 0 00 iopmod 0x5000 r/w i/o port mode register 0x00000000 iop con 0 0x5004 r/w i/o port control 0 register 0x00000000 iop con1 0x5008 r/w i /o port control 1 register 0x00000000 i/o ports iopdata 0x500 c r/w i/o port data register undefined spicfg 0x5804 r/w spi configuration register 0x0000000f spists 0x5808 r spi stat us register 0x00000000 spicmd 0x580c r/w spi command register 0x00000000 txchr 0x5810 r/w spi transmit register 0x00000000 spi rxchr 0x581c r spi receive register 0x00000000 intmod 0x4000 r/w interrupt mode register 0x00000000 int pnd 0x4004 r/w interrupt pending register 0x00000000 intmsk 0x4008 r/w interrupt mask register 0x00 f fffff intpri0 0x400c r/w interrupt priority register 0 0x0 3020100 intpri1 0x4010 r/w interrupt priority register 1 0x07060504 intpri2 0x4014 r/w int errupt priority register 2 0x0b0a0908 intpri3 0x4018 r/w interrupt priority register 3 0x0f0e0d0c intpri4 0x401c r/w interrupt priority register 4 0x 1312 1110 intpri5 0x4020 r/w interrupt priority register 5 0x00 161514 intoffset 0x4024 r interrupt o ffset address register 0x000000 5c int pndpri 0x4028 r interrupt pending priority register 0x000000 00 interrupt controller int pndtst 0x402 c w interrupt pending test register 0x000000 00
S5N8947 (mcu for dsl) electronics dsl group page : 44 october 26 , 2001 rev 1.8 samsung electronics intoset_fiq 0x4030 r fiq interrupt offset register 0x0000005 c intoset_irq 0x4034 r irq interrupt offset register 0x0000005 c iiccon 0xf000 r/w i 2 c bus control status register 0x000000 00 iicbuf 0xf004 r/w i 2 c bus shift buffer register undefined iicps 0xf008 r/w i 2 c bus prescaler register 0x00000000 i 2 c bus iiccount 0xf00c r i 2 c bus pr escaler counter register 0x00000000 gdmacon0 0xb000 r/w gdma channel 0 control register 0x00000000 gdmacon1 0xc000 r/w gdma channel 1 control register 0x00000000 gdmasrc0 0xb004 r/w gdma source address register 0 undefined gdmadst0 0xb008 r/w g dma destination address register 0 undefined gdmasrc1 0xc004 r/w gdma source address register 1 undefined gdmadst1 0xc008 r/w gdma destination address register 1 undefined gdmacnt0 0xb00c r/w gdma channel 0 transfer count register undefined gdma gdmacnt 1 0xc00c r/w gdma channel 1 transfer count register undefined ulcon 0xd000 r/w uart line control register 0x xxxxxx 00 ucon 0xd004 r/w uart control register 0x xxxxxx 00 ustat 0xd008 r uart status register 0x xxxxxx c0 utxbuf 0xd00c w uart transmit h olding register undefined urxbuf 0xd010 r uart receive buffer register undefined uart ubrdiv 0xd014 r/w baud rate divisor register 0xxxxxxx00 tmod 0x6000 r/w timer mode register 0x00000000 tdata0 0x6004 r/w timer 0 data register 0x00000000 tdata 1 0x6008 r/w timer 1 data register 0x00000000 tdata 2 0x600 c r/w timer 2 data register 0x00000000 tcnt0 0x60 10 r/w timer 0 count register 0x ffffffff tcnt1 0x601 4 r/w timer 1 count register 0x ffffffff tcnt2 0x601 8 r/w timer 2 count register 0x fffffff f wdcon 0x601c r/w watchdog timer control register 0x ffffff00 timers wdcnt 0x6020 r watchdog timer count register 0x ffffffff
electronics S5N8947 (mcu for dsl) page : 45 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 8. electric characteristics 8.1. a bsolute m aximum r atings parameter symbol rating units 1.8v v dd 2.7 supply voltage v dd 3.3v v dd 3.8 v 1.8v input buffer 2.7 dc input voltage v in 1.8v interface 3.3v tolerant input buffer 3.8 v operating temperature t opr ? 40 to 85 o c storage temperature t stg ? 65 to 150 o c table 4 absolute maximum ratings 8.2. r ecommended op erating conditions parameter symbol rating units 1.8v v dd 1.8 0.15 supply voltage v dd /v dda 3.3v v dd 3.3 0.3 v oscillator frequency f osc 12 mhz external loop filter capacitance l f 320 pf industrial temperature range t a - 40 to 85 o c table 5 recommaended operating conditions parameter symbol min typ max units power dissipation p d 300 ? table 6 power dissipation notes it is strongly recommended that all the su pply pins ( v dd /v dda ) be powered from the same source to avoid power latch - up.
S5N8947 (mcu for dsl) electronics dsl group page : 46 october 26 , 2001 rev 1.8 samsung electronics 8.3. dc e lectrical c haracteristics v dd = 1.8 0.15 v, v ext = 3.0 0.3 v, t a = - 40 to 85 c (in case of 3.3 v - tolerant i/o) parameter symbol conditions min typ max unit high level input voltage lvcmos i /f v ih ? 1.27 ? ? v low level input voltage lvcmos i/f v il ? ? ? 0.57 v switching threshold vt lvcmos ? 0.55v dd ? v schm itt trigger positive - going threshold vt+ lvcmos ? ? 1.27 ? schmitt trigger negative - going threshold vt ? lvcmos 0.57 ? ? ? input buffer ? 10 ? 10 high level input current input buffer with pull - up i ih v in = v dd 5 18 40 a inp ut buffer ? 10 ? 10 low level input current input buffer with pull - up i lh v in = v ss ? 40 ? 18 ? 5 a type b1 to b12 i oh = ? 1 a v dd ? 0.05 ? ? v type b1 i oh = ? 1 ma type b2 i oh = ? 2 ma type b4 i oh = ? 4 ma high level output v oltage type b6 v oh i oh = ? 6 ma 1.2 type b1 to b12 i ol = 1 a 0.05 v type b1 i ol = 1 ma type b2 i ol = 2 ma type b4 i ol = 4 ma low level output voltage type b6 v ol i ol = 6 ma 0.45 tri - state output leakage current i oz v out = v ss or v dd ? 10 10 a maximum operating current i dd v dd = 3.6 v , f mclk = 50mhz 100 a table 7 dc electrical characteristics
electronics S5N8947 (mcu for dsl) page : 47 dsl group samsung electronics october 26 , 2001 rev 1.8 confidential 9. package dimension this section describes the mechanical data for the S5N8947 2 08 - pin l qfp package. 208 - l qfp - 2828 pac kage dimensions
S5N8947 (mcu for dsl) electronics dsl group page : 48 october 26 , 2001 rev 1.8 samsung electronics figure 19 208 - lqfp - 2828 package dimensions

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